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VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7133
Features
* 802.3z Gigabit Ethernet Compliant 1.25 Gb/s Transceiver * ANSI X3T11 Fibre Channel Compliant 1.0625 Gb/s Transceiver * 0.98 to 1.36 Gb/s Full Duplex Operation * 10 Bit TTL Interface for Transmit and Receive Data
10-bit Transceiver for Fibre Channel and Gigabit Ethernet
* TTL or PECL Reference Clock * Automatic Lock-to-Reference * RX Cable Equalization and Signal Detect * JTAG Access Port for Testability * 64-pin, 10mm PQFP Packaging * Single +3.3V Supply, 650 mW
General Description
The VSC7133 is a full-speed Fibre Channel and Gigabit Ethernet Transceiver with industry-standard pinouts. It accepts 10-bit 8B/10B encoded transmit data, latches it on the rising edge of the TTL/PECL REFCLK and serializes it onto the TX PECL differential outputs at a baud rate which is ten times the REFCLK frequency. Serial data input on the RX PECL differential inputs is resampled by the Clock Recovery Unit, deserialized onto the 10-bit receive data bus synchronously to complementary divide-by-twenty clocks. The VSC7133 receiver detects "Comma" characters for frame alignment. An analog/digital signal detection circuit indicates that a valid signal is present on the RX input. A cable equalizer compensates for Inter Symbol Interference in order to increase maximum cable distances. The VSC7133 contains PLL circuitry for synthesis of the baud-rate transmit clock, and extraction of the clock from the received serial stream. The VSC7133 is similar to the VSC7123 but has either a TTL or a PECL reference clock.
VSC7133 Block Diagram
R(0:9)
10
QD
Serial to Q Parallel D /10
QD 2:1
RX+ RX-
RCLK RCLKN COMDET ENCDET EWRAP SIGDET T(0:9) REFCLKP REFCLKN
10
Clock /20 Recovery Comma Detect Signal Detect Parallel to Serial
DQ
DQ
TX+ TX-
x10 Clock Multiply
NOT SHOWN: JTAG Boundary Scan
G52187-0 Rev. 2.4 1/17/00
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 1
VITESSE
SEMICONDUCTOR CORPORATION
10-bit Transceiver for Fibre Channel and Gigabit Ethernet
Advance Product Information
VSC7133
Functional Description
Clock Synthesizer The VSC7133 clock synthesizer multiplies the reference frequency provided on the REFCLK pin by 10 to achieve a baud rate clock between 0.98 and 1.36 GHz. The on-chip PLL uses a single external 0.1uF capacitor to control the Loop Filter. The REFCLK is either TTL or LV PECL. If TTL, connect the TTL input to REFLKP and leave REFCLKN open, it is biased for a TTL switch level. If PECL, connect both REFCLKP and REFCLKN. Serializer The VSC7133 accepts TTL input data as a parallel 10 bit character on the T(0:9) bus, which is latched into the input register on the rising edge of REFCLK. This data is serialized and transmitted on the TX PECL differential outputs at a baud rate that is ten times the frequency of the REFCLK, with bit T0 transmitted first. User data should be encoded using 8B/10B block code or equivalent. Transmission Character Interface An encoded byte is 10 bits and is referred to as a transmission character. The 10 bit interface on the VSC7133 corresponds to a transmission character. This mapping is illustrated in Figure 1. Figure 1: Transmission Order and Mapping of an 8B/10B Character
Parallel Data Bits 8B/10B Bit Position Comma Character
T9 j X
T8 h X
T7 g X
T6 f 1
T5 i 1
T4 e 1
T3 d 1
T2 c 1
T1 b 0
T0 a 0
Last Data Bit Transmitted
First Data Bit Transmitted
Clock Recovery The VSC7133 accepts differential high speed serial inputs on the RX+/RX- pins, extracts the clock and retimes the data. Equalizers are included in the receiver to open the data eye and compensate for InterSymbol Interference (ISI) which may be present in the incoming data. The serial bit stream should be encoded so as to provide DC balance and limited run length by an 8B/10B encoding scheme. The Clock Recovery Unit (CRU) is completely monolithic and requires no external components. For proper operation, the baud rate of the data stream to be recovered should be within +200 ppm of ten times the REFCLK frequency. For example, Gigabit Ethernet systems would use 125 MHz oscillators with a +/-100ppm accuracy resulting in +/-200 ppm between VSC7133 pairs.
Page 2
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52187-0 Rev. 2.4 1/17/00
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7133
10-bit Transceiver for Fibre Channel and Gigabit Ethernet
Deserializer The recovered serial bit stream is converted into a 10-bit parallel output character. The VSC7133 provides complementary TTL recovered clocks, RCLK and RCLKN, which are one twentieth of the serial baud rate. The clocks are generated by dividing down the high-speed recovered clock which is phase locked to the serial data. The serial data is retimed, deserialized and output on R(0:9). The parallel data will be captured by the adjoining protocol logic on the rising edges of RCLK and RCLKN. If serial input data is not present, or does not meet the required baud rate, the VSC7133 will continue to produce a recovered clock so that downstream logic may continue to function. The RCLK/RCLKN output frequency under these circumstances will differ from its expected frequency by no more than +1%. Word Alignment The VSC7133 provides 7-bit comma character recognition and data word alignment. Word synchronization is enabled by asserting ENCDET HIGH. When synchronization is enabled, the receiver examines the recovered serial data for the presence of the "Comma" character. This pattern is "0011111XXX", where the leading zero corresponds to the first bit received. The comma sequence is not contained in any normal 8B/10B coded data character or pair of adjacent characters. It occurs only within special characters, known as K28.1, K28.5 and K28.7, which are defined for synchronization purposes. Improper alignment of the comma character is defined as any of the following conditions: 1) The comma is not aligned within the 10-bit transmission character such that R(0..6) = "0011111". 2) The comma straddles the boundary between two 10-bit transmission characters. 3) The comma is properly aligned but occurs in the received character presented during the rising edge of RCLK rather than RCLKN. When ENCDET is HIGH and an improperly aligned comma is encountered, the recovered clock is stretched, never slivered, so that the comma character and recovered clocks are aligned properly to R(0:9). This results in proper character and word alignment. When the parallel data alignment changes in response to a improperly aligned comma pattern, some data which would have been presented on the parallel output port may be lost. Also, the first Comma pattern may be lost or corrupted. Subsequent data will be output correctly and properly aligned. When ENCDET is LOW, the current alignment of the serial data is maintained indefinitely, regardless of data pattern. On encountering a comma character, COMDET is driven HIGH. The COMDET pulse is presented simultaneously with the comma character and has a duration equal to the data, or half of an RCLK period. The COMDET signal is timed such that it can be captured by the adjoining protocol logic on the rising edge of RCLKN. Functional waveforms for synchronization are given in Figure 2 and Figure 3. Figure 2 shows the case when a comma character is detected and no phase adjustment is necessary. It illustrates the position of the COMDET pulse in relation to the comma character on R(0:9). Figure 3 shows the case where the K28.5 is detected, but it is misaligned so a change in the output data alignment is required. Note that up to three characters prior to the comma character may be corrupted by the realignment process.
G52187-0 Rev. 2.4 1/17/00
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 3
VITESSE
SEMICONDUCTOR CORPORATION
10-bit Transceiver for Fibre Channel and Gigabit Ethernet
Advance Product Information
VSC7133
Signal Detection: The receiver has an output, SIGDET, indicating, when HIGH, that the RX input contains a valid Fibre Channel or Gigabit Ethernet signal. A combination of one analog and three digital checks are used to determine if the incoming signal contains valid data. SIGDET is updated every four RCLKs. If during the current period, all the four criteria are met, SIGDET will be HIGH during the next 4 RCLK period. If during the current period, any of the four criteria is not met, SIGDET will be LOW during the next 4 RCLK period. 1.) Analog transition detection is performed on the input to verify that the signal swings are of adequate amplitude. The RX+/- input buffer contains a differential voltage comparator which will go high if the differential peak-to-peak amplitude is greater than 400mV or LOW if under 200mV. If the amplitude is between 200 and 400mV, the output is indeterminate. 2.) Data on R(0:9) is monitored for all zeros (0000000000). If this pattern is encountered during the current RCLK interval, the SIGDET output will go LOW during the next four RCLK interval. 3.) Data on R(0:9) is monitored for all ones (1111111111). If this pattern is encountered during the current RCLK interval, the SIGDET output will go LOW during the next four RCLK interval. 4.) Data on R(0:9) is monitored for K28.5- (0011111010). Unlike previous patterns, the interval during which a K28.5- must occur is 64K+24 10-bit characters in length. Valid Fibre Channel or Gigabit Ethernet data will contain a K28.5- character during any period of this length. If a K28.5- is not detected during the monitoring period , SIGDET will go LOW during the next period. The behavior of SIGDET is affected by EWRAP and ENCDET as shown below. Table 1: Signal Detect Behaviour EWRAP
0 0 1 1
ENCDET
0 1 0 1
Transition Detect
Enabled Enabled Enabled Enabled
All Zeros/ All Ones
Enabled Enabled Disabled Disabled
K28.5 Presence
Enabled Disabled Disabled Disabled
Mode
Normal COMDET Disable Loopback Loopback
COMDET, RCLK, RCLKN and R(0:9) are unaltered by SIGDET.
JTAG Access Port A JTAG Access Port is provided to assist in board-level testing. Through this port most pins can be accessed or controlled and all TTL outputs can be tri-stated. A full description of the JTAG functions on this device is available in "VSC7123/VSC7133 JTAG Access Port Functionality".
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(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52187-0 Rev. 2.4 1/17/00
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7133
10-bit Transceiver for Fibre Channel and Gigabit Ethernet
Figure 2: Detection of a Properly Aligned Comma Character
RCLK RCLKN
COMDET
R(0:9)
K28.5
TChar
TChar
TChar
TChar: 10 bit Transmission Character
Figure 3: Detection and Resynchronization of an Improperly Aligned Comma
Receiving Two Consecutive K28.5+TChar Transmission Words Clock Stretching
RCLK RCLKN
COMDET
R(0:9)
Potentially Corrupted
K28.5
TChar
TChar
TChar
K28.5
TChar
G52187-0 Rev. 2.4 1/17/00
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 5
VITESSE
SEMICONDUCTOR CORPORATION
10-bit Transceiver for Fibre Channel and Gigabit Ethernet
Advance Product Information
VSC7133
Figure 4: Transmit Timing Waveforms
AC Characteristics
REFCLK
T1 T2
T(0:9)
Data Valid
Data Valid
Data Valid
Table 2: Transmit AC Characteristics Parameters T1 T2 TSDR,TSDF TLAT Description T(0:9) Setup time to the rising edge of REFCLK T(0:9) hold time after the rising edge of REFCLK TX+/TX- rise and fall time Latency from rising edge of REFCLK to T0 appearing on TX+/TXTotal data output jitter Serial data output deterministic jitter (p-p) Min
1.5
Max
--
Units
ns.
Conditions Measured between the valid data level of T(0:9) to the 1.4V point of REFCLK
1.0 --
-- 300 8bc+ 4ns
ns. ps.
20% to 80%, 50 Ohm load to VDD-2.0 bc = Bit clocks ns = Nano second
8bc
ns
Transmitter Output Jitter Allocation
TJ TDJ -- -- 192 80 ps. ps.
IEEE 802.3z Clause 38.68, IEEE 802.3z Clause 38.68,
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G52187-0 Rev. 2.4 1/17/00
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7133
Figure 5: Receive Timing Waveforms
T4
10-bit Transceiver for Fibre Channel and Gigabit Ethernet
RCLK
T3
RCLKN
T1 T2
Data Valid
R(0:9)
Data Valid
Data Valid
Table 3: Receive AC Characteristics Parameters T1 T2 T3 T4 T R , TF RLAT TLOCK* Description TTL Outputs Valid prior to RCLK/RCLKN rise TTL Outputs Valid after RCLK or RCLKN rise Delay between rising edge of RCLK to rising edge of RCLKN Period of RCLK and RCLKN R(0:9), COMDET, SIGDET, RCLK and RCLKN rise and fall time Latency from RX to R(0:9) Data acquisition lock time Min.
4.0 3.0 3.0 2.0 10 x TRX -500 1.98 x TREFCLK --
Max.
-- -- -- -- 10 x TRX +500 2.02 x TREFCLK 2.4
Units
ns ns
Conditions @ 1.0625Gb/s @ 1.25Gb/s @ 1.0625Gb/s @ 1.25Gb/s TRX is the bit period of the incoming data on Rx. Whether or not locked to serial data. Between VIL(MAX) and VIH(MIN), into 10 pf. load. bc = Bit clock ns = Nano second 8B/10B IDLE pattern. bc= bit clocks
ps
ps
ns bc ns bc
12 bc + 1 ns --
13 bc + 9 ns 1400
* Note: Probability of recovery for data acquisition is 95% per Section 5.3 of FC-PH rev. 4.3
G52187-0 Rev. 2.4 1/17/00
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
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VITESSE
SEMICONDUCTOR CORPORATION
10-bit Transceiver for Fibre Channel and Gigabit Ethernet
Advance Product Information
VSC7133
Figure 6: REFCLK Timing Waveforms
TL REFCLKP REFLKN TR
TH VIH(MIN) VIL(MAX) TF
Table 4: Reference Clock Requirements Parameter Description Min Max Units Conditions Range over which both transmit and receive reference clocks on any link may be centered Maximum frequency offset between transmit and receive reference clocks on one link Measured at 1.5V Between VIL(MAX) and VIH(MIN)
FR
Frequency Range
98
136
MHz
FO DC TR,TF
Frequency Offset REFCLK duty cycle REFCLK rise and fall time
-200
200
ppm.
35 --
65 1.5
% ns.
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(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52187-0 Rev. 2.4 1/17/00
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7133
10-bit Transceiver for Fibre Channel and Gigabit Ethernet
Figure 7: Parametric Measurement Information
Serial Input Rise and Fall Time
80% 20%
TTL Input and Output Rise and Fall Time
VIH(MIN)
VIL(MIN)
Tr
Tf
Tr
Tf
Receiver Input Eye Diagram Jitter Tolerance Mask
Bit Time
Amplitude
24% Minimum Eye Width%
Parametric Test Load Circuit Serial Output Load TTL A.C. Output Load
Z0 = 50 or 75W
50 or 75W
10 pF
VDD - 2.0V
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(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
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VITESSE
SEMICONDUCTOR CORPORATION
10-bit Transceiver for Fibre Channel and Gigabit Ethernet
Advance Product Information
VSC7133
Absolute Maximum Ratings (1)
Power Supply Voltage, (VDD) ............................................................................................................-0.5V to +4V DC Input Voltage (PECL inputs)............................................................................................ -0.5V to VDD +0.5V DC Input Voltage (TTL inputs) ......................................................................................................-0.5V to +5.5V DC Output Voltage (TTL Outputs)........................................................................................ -0.5V to VDD + 0.5V Output Current (TTL Outputs) ................................................................................................................. +/-50mA Output Current (PECL Outputs)................................................................................................................+/-50mA Case Temperature Under Bias .........................................................................................................-55o to +125oC Storage Temperature..................................................................................................................... -65oC to +150oC Maximum Input ESD (Human Body Model).............................................................................................. 2000 V Maximum Input ESD (Charge Device Model) ........................................................................................... 1000 V
Recommended Operating Conditions
Power Supply Voltage, (VDD) ................................................................................................................+3.3V+5% Operating Temperature Range ............................................................ 0oC Ambient to +95oC Case Temperature
Notes: (1) CAUTION: Stresses listed under "Absolute Maximum Ratings" may be applied to devices one at a time without causing permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended periods may affect device reliability.
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G52187-0 Rev. 2.4 1/17/00
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7133
DC Characteristics (Over recommended operating conditions).
Parameters VOH VOL VIH VIL IIH IIL
VOUT751 VOUT501 VIN1
10-bit Transceiver for Fibre Channel and Gigabit Ethernet
Description Output HIGH voltage (TTL) Output LOW voltage (TTL) Input HIGH voltage (TTL) Input LOW voltage (TTL) Input HIGH current (TTL) Input LOW current (TTL) TX Output differential peakto-peak voltage swing TX Output differential peakto-peak voltage swing RX Input differential peakto-peak input sensitivity Supply voltage Power dissipation Supply Current (All Supplies) Analog Supply Current
Min
2.4 -- 2.0 0 -- -- 1200 1000 300 3.14 -- -- --
Typ
-- -- -- -- 50 -- -- -- -- -- 650 190 --
Max
-- 0.5 5.5 0.8 500 -500 2200 2200 2600 3.47 900 260 100
Units
V V V V A A mVp-p mVp-p mVp-p V mW mA mA
Conditions IOH = -1.0 mA IOL = +1.0 mA 5V Tolerant Inputs -- VIN =2.4V VIN =0.5V 75 to VDD - 2.0 V (TX+) - (TX-) 50 to VDD - 2.0 V (TX+) - (TX-) Internally biased to Vdd/2 (RX+) - (RX-) 3.3V5% Outputs open, VDD = VDD max Outputs open, VDD = VDD max
VDD
PD IDD IDDA
1 NOTE:
VDDA = VDDA max
Refer to Application Note, AN-37, for differential measurement techniques.
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(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
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VITESSE
SEMICONDUCTOR CORPORATION
10-bit Transceiver for Fibre Channel and Gigabit Ethernet
Advance Product Information
VSC7133
Figure 8: Input Structures
VDDD
VDDD
3K
INPUT INPUT
4K
3K GND
INPUT
4K GND
TTL Inputs (not REFCLK)
VDD
+3.3 V
High Speed Input (RX+/RX-)
12.6K
VDDP
VDDD
REFCLK
9.3K 12.6K 9.3K GND
TX+ TX-
GND
Hi Speed Outputs (TX+/-)
REFCLK TTL Input
VDDT
OUTPUT
VSST
VSSD
TTL Outputs
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G52187-0 Rev. 2.4 1/17/00
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7133
Package Pin Descriptions
Figure 9: Pin Diagram
10-bit Transceiver for Fibre Channel and Gigabit Ethernet
VDDD
VDDD
TRSTN
VDDD
VDDP
VDDP
VSSD
VSSD
TMS
VSSD
TX+
63 VSSD T0 T1 T2 VDDD T3 T4 T5 T6 VDDD T7 T8 T9 VSSD VSSA CAP0 15 17 19 13 11 9 7 5 3 1
61
TX-
59
57
55
53
RX-
51
49 TDI 47 COMDET VSST 45 R0 R1 43 R2 VDDT 41 R3 R4 39 R5 R6 37 VDDT R7 35 R8 R9
TCK
RX+
N/C
21
23
25
27
29
31
33
VSST
(Top View)
REFCLKP ENCDET SIGDET EWRAP CAP1 RCLKN RCLK VDDA VDDD TDO VDDD VSSD VSSD REFCLKN VDDT VSST
Table 5: Pin Identification Pin #
2,3,4,6 7,8,9,11 12,13
Name
T0,T1,T2,T3 T4,T5,T6,T7 T8,T9
Description INPUTS - TTL 10-bit transmit character. Parallel data on this bus is clocked in on the rising edge of REFCLK. The data bit corresponding to T0 is transmitted first.
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VITESSE
SEMICONDUCTOR CORPORATION
10-bit Transceiver for Fibre Channel and Gigabit Ethernet
Table 5: Pin Identification Pin # Name
Advance Product Information
VSC7133
Description
22 23
REFCLKP REFCLKN
INPUT - Differential PECL or Single-Ended TTL This rising edge of this clock latches T(0:9) into the input register. It also provides the reference clock, at one tenth the baud rate to the PLL. If TTL, connect to REFCLKP but leave REFCLKN open. If PECL, connect both REFCLKP and REFCLKN. OUTPUTS - Differential PECL (AC Coupling recommended) These pins output the serialized transmit data when EWRAP is LOW. When EWRAP is HIGH, TX+ is HIGH and TX- is LOW. OUTPUTS - TTL 10-bit received character. Parallel data on this bus is clocked out on the rising edges of RCLK and RCLKN. R0 is the first bit received on RX+/RX-. INPUT - TTL LOW for Normal Operation. When HIGH, an internal loopback path from the transmitter to the receiver is enabled and the TX outputs are held HIGH. INPUTS - Differential PECL (AC Coupling recommended) The serial receive data inputs selected when EWRAP is LOW. Internally biased to VDD/2, with 3.3K resistors from each input pin to VDD and GND. OUTPUT - Complementary TTL Recovered clocks derived from one twentieth of the RX+/- data stream. Each rising transition of RCLK or RCLKN corresponds to a new word on R(0:9). INPUT - TTL Enables COMDET and word resynchronization when HIGH. When LOW, keeps current word alignment and disables COMDET. OUTPUT - TTL This output goes HIGH for half of an RCLK period to indicate that R(0:9) contains a Comma Character (`0011111XXX'). COMDET will go HIGH only during a cycle when RCLKN is rising. COMDET is enabled by ENCDET being HIGH. OUTPUT - TTL SIGnal DETect. This output goes HIGH when the RX input contains a valid Fibre Channel or Gigabit Ethernet signal. A LOW indicates an invalid signal. ANALOG: Differential capacitor for the CMU's VCO. 0.1 uF nominal. INPUT - TTL: JTAG clock input. Not normally connected. INPUT - TTL: JTAG data input. Not normally connected. INPUT - TTL: JTAG mode select input. Normally tied to VDDD INPUT - TLL: JTAG reset input. Tie to VSSD for normal operation. OUTPU - TTL: JTAG data output. Normally tri-stated. Analog Power Supply.
62, 61 45,44,43,41 40,39,38,36 35,34 19
TX+, TXR0,R1,R2,R3 R4,R5,R6,R7 R8,R9 EWRAP
54, 52
RX+, RX-
31, 30
RCLK, RCLKN
24
ENCDET
47
COMDET
26 16, 17 49 48 55 56 27 18
SIGDET CAP0, CAP1 TCK TDI TMS TRSTN TDO VDDA
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Advance Product Information
VSC7133
Table 5: Pin Identification Pin #
15 5,10,20,28 50,57,59 1,14,21,25 51,58,64 29, 37, 42 32, 33, 46 60,63 53
10-bit Transceiver for Fibre Channel and Gigabit Ethernet
Name
VSSA VDDD VSSD VDDT VSST VDDP N/C
Description Analog Ground Digital Logic Power Supply Digital Logic Ground TTL Output Power Supply TTL Output Ground PECL I/O Power Supply No Connection.
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VITESSE
SEMICONDUCTOR CORPORATION
10-bit Transceiver for Fibre Channel and Gigabit Ethernet
Advance Product Information
VSC7133
Package Information: 64-pin PQFP
F G
64 49
Item
A
48
10 mm
2.45 2.00 0.22 13.20 10.00 13.20 10.00 0.88 0.50
Tolerance
MAX +0.10/-0.05 0.05 0.25 0.10 0.25 0.10 +0.15/-0.10 BASIC
1
A2 E F G I H H I J
16 33
K
17
10o TYP
32
A
A2
100 TYP
K
0.30 RAD. TYP.
A
0.20 RAD. TYP.
STANDOFF
0.25 MAX.
0.17 MAX. 0.25 J
0o- 8o
0.102 MAX. LEAD COPLANARITY
E
NOTES: Drawing not to scale. All units in mm unless otherwise noted.
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G52187-0 Rev. 2.4 1/17/00
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SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7133
Thermal Considerations
10-bit Transceiver for Fibre Channel and Gigabit Ethernet
The VSC7133 is packaged in a 10mm, thermally enhanced PQFP with an internal heat spreader. These packages use industry-standard EIAJ footprints, but have been enhanced to improve thermal dissipation. The construction of the packages are shown below.
Figure 10: Package Cross Section
Plastic Molding Compound
Internal Heat Spreader Insulator
Lead
Table 6: Thermal Resistance Symbol jc ca ca-100 ca-200 ca-400 ca-600
Bond Wire
Die
Description Thermal resistance from junction to case Thermal resistance from case to ambient in still air including conduction through the leads. Thermal resistance from case to ambient with 100 LFM airflow Thermal resistance from case to ambient with 200 LFM airflow Thermal resistance from case to ambient with 400 LFM airflow Thermal resistance from case to ambient with 600 LFM airflow 10 50 41 37 32 28
10mm
Units
o o
C/W C/W
oC/W oC/W oC/W oC/W
The VSC7133 is designed to operate with a case temperature up to 95oC. The user must guarantee that the case temperature specification is not violated. With the thermal resistances shown above, the 10mm Thermally Enhanced PQFP can operate in still air ambient temperatures of 50oC [50oC = 95oC - 0.9W * 50]. If the ambient air temperature exceeds these limits then some form of cooling through a heatsink or an increase in airflow must be provided.
Moisture Sensitivity Level
This device is rated at with a Moisture Sensitivity Level 3 rating. Refer to Application Note AN-20 for appropriate handling procedures.
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VITESSE
SEMICONDUCTOR CORPORATION
10-bit Transceiver for Fibre Channel and Gigabit Ethernet
Advance Product Information
VSC7133
Ordering Information
The part number for this product is formed by a combination of the device number and the package style:
VSC7133QU Device Type: VSC7133: 10-bit Transceiver Package Style (64-pin) QU: 10mm PQFP
Marking Information
The package is marked with three lines of text as shown below.
Figure 11: Package Marking Information
Pin 1 Identifier VITESSE Part Number Date Code VSC7133QU ####AAAA Package Suffix Lot Tracking Code
Notice
This document contains information about a product during its fabrication or early sampling phase of development. The information contained in the document is based on design targets, simulation results or early prototype test results. Characteristic data and other specifications are subject to change without notice. Therefore the reader is cautioned to confirm that this datasheet is current prior to design or order placement.
Warning
Vitesse Semiconductor Corporation's product are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without written consent is prohibited.
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(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52187-0 Rev. 2.4 1/17/00

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